The principle of signal folding structures is as follows: the analog input signal to be converted is applied to the input of a group of differential amplifiers receiving regularly distributed reference voltages; these amplifiers provide so-called “folded” signals having an amplitude which varies nearly sinusoidally with the amplitude of the input signal, with a period which is defined by the separation of the reference voltages distributed in a useful range of amplitudes to be converted. The number of reference voltages in a group defines the number of periods of the folded-signal curve in this useful range. The bits of the analog-digital conversion for an input voltage value are defined by whether the signal arising from the folding structure belongs to one of the intervals defined by the zero crossings of the folded-signal curve.
The reference voltages are produced by one or more resistor bridges supplied by a reference current which is constant or is supplied between two reference voltages. The precision structures intended for high-resolution conversion are most often differential and the case of differential structures will be described hereinafter.
FIG. 1 represents the basic setup of a signal folding structure. It comprises two elementary differential circuits each consisting of a double differential pair of transistors which establish currents dependent on the difference between the voltage to be converted and reference voltages, and two load circuits which convert these currents into voltage. A signal folding block comprises several groups of two differential circuits and the associated load circuits. A folding structure can comprise several folding blocks. The number of circuits in a block determines the number of folding periods of the folding curve engendered by this block. The number of blocks determines the number of simultaneously engendered parallel folding curves. The folding curves are spaced regularly apart and their zero crossings are precisely defined with respect to the voltage references provided by the resistor bridges.
The differential circuits each comprise four inputs (two pairs of differential inputs) and two outputs; the outputs of adjacent circuits are linked to one another in a manner that will be detailed further on. Each load circuit may be considered to comprise an input and an output; the input is linked to a differential-circuit output; the output is linked to an output conductor of the folding block.
As will be seen, there are in one and the same folding block load circuits of odd rank whose input is connected to a first output of a differential circuit (and connected at the same time to a second output of an immediately preceding differential circuit in the series) and load circuits of even rank whose input is connected to a second output of the differential circuit (and connected at the same time to a first output of an immediately following differential circuit). All the outputs of load circuits of odd rank are connected to a first output conductor of the folding block, and all the outputs of load circuits of even rank are connected to a second output conductor of the block.
FIG. 1 represents an exemplary setup of a group of two adjacent differential circuits CRj and CRj+1 and of two corresponding load circuits CHj and CHj+1 connected as indicated above and intended to be linked to other differential circuits in one and the same folding block. The index j represents the rank of the consecutive circuits in the series making up a block.
A differential circuit such as CRj comprises two differential pairs of transistors; each pair is supplied by a constant current source I0. The current is the same for the two pairs and for all the differential circuits. The transistors of a pair are linked by their emitters to this current source. Hereinafter it will be considered that the transistors are bipolar transistors, the invention being usable with MOS transistors also.
The circuit CRj possesses four inputs which are the bases of the four transistors making up the two pairs. The first pair receives respectively a signal voltage to be converted Vinp and a reference voltage Vrefpj. The second pair receives respectively a signal voltage to be converted Vinn and a reference voltage Vrefnj. The group of voltages Vinp, Vinn constitutes the differential input voltage to be converted, to be compared with differential reference voltages defined by the voltages Vrefpj, Vrefnj.
The same voltages Vinp and Vinn are applied to the corresponding transistors of all the differential circuits. They can originate from a sample-and-hold unit or from a simple differential amplifier. The reference voltages are different for the various differential circuits: they are voltages Vrefpj+1 and Vrefnj+1 for the circuit CRj+1 of rank j+1. The reference voltages for the various differential circuits are regularly distributed between a low value and a high value and they originate from the intermediate taps of a resistor bridge (not represented).
The collector of the transistor which receives the input voltage in a differential pair is linked to the collector of the transistor which receives a reference voltage on the other pair. The collectors thus coupled in twos constitute two outputs S1j and S2j of the differential circuit CRj.
These outputs S1j and S2j serve on the one hand for the connection between the consecutive differential circuits and on the other hand for the connection to the load circuits.
The first output S1j of the differential circuit of rank j is connected to the second output (not represented) of the immediately preceding differential circuit, of rank j−1 (if it exists). Reciprocally, the second output S2j of the differential circuit of rank j is linked to the first output of the differential circuit of immediately following rank j+1 (if it exists).
The load circuit of rank j (CHj) has its input Ecj linked to the first output S1j of the differential circuit CRj of like rank.
It follows from this that each load circuit is shared between two adjacent differential circuits since a load circuit is connected at one and the same time to the first output of the circuit of rank j and to the second output of the circuit of rank j−1.
The output Scj of the load circuit of rank j is linked to an output conductor Ap, but the output of the load circuit of immediately following rank is linked to another output conductor An. These two conductors are common to the whole of the folding block and constitute the two outputs (providing a folded signal) of the block. The outputs of the load circuits of the succession are alternately connected to the conductor An and to the conductor Ap. For example, all the load circuits of odd rank have their output linked to the conductor Ap and all the load circuits of even rank have their output linked to the conductor An.
The load circuits are moreover all identical; the load circuit of rank j is, in this example, made up of two transistors which are respectively a cascode transistor and a follower transistor; the cascode transistor has its emitter linked to the input Ecj, its base linked to a fixed bias potential common to the whole of the folding block, and its collector linked by a resistor (identical for all the circuits) supplied by a supply voltage; the follower transistor has its base linked to the collector of the cascode transistor, its emitter linked to a constant current source of value and its collector linked to a supply voltage. The output Scj of the load circuit is taken on the emitter of the follower transistor. The cascode transistor serves to prevent the voltage on the outputs of the differential circuit varying overly as a function of the input signal level Vinp, Vinn.
FIG. 2 represents the general organization of a folding structure with several blocks each comprising several differential circuits and the associated loads. The example is given for a structure which engenders four folding curves (and which comprises for this purpose four blocks represented one below the other), each folding curve comprising two complete periods in a useful range of analog voltages to be converted.
To engender four different curves, the blocks receive different voltages originating either from a respective resistor bridge for each block or from a common bridge for all the blocks, the successive taps along the bridge serving successively for the various blocks. The resistor bridge or bridges are not represented so as not to overburden the diagram.
Each block comprises a pair of outputs: Ap, An for the first block, Bp, Bn for the second block, and Cp, Cn, Dp, Dn for the last two.
These outputs provide folded signals visible in FIG. 3: output signal folded as a function of the input voltage. Each block provides a respective folded curve A, B, C, D. Curve A is a representation of the voltage obtained between the output conductors Ap and An of the first block. Curves B, C, D represent the output voltages of the other blocks. The folding blocks are usable in an input range between a low voltage Vb and a high voltage Vh. In this range the folded curves of sinusoidal shape are truly regular and their intersections are spaced regularly apart. Outside of this range, the curves are deformed by edge effects related to the fact that the loads of the differential circuits of the ends of the block are not shared between two differential circuits.
The number of differential circuits required in each block to engender two folding periods in the useful range Vb, Vh is four. This is because to each differential circuit there corresponds one zero crossing of the folding curve and four zero crossings are necessary to complete the two periods. However, the first folding block comprises five differential circuits and not four since the folding curve A comprises in total five zero crossings if the zero crossing at Vb and the zero crossing at Vh are included; these zero-crossings for Vb and Vh are required in order to define the limit values Vb, Vh of the useful range.
Consequently, returning to the diagram of FIG. 2, it is possible to consider that the circuits required for the formulation of the four folding curves A, B, C, D each with two complete periods are:                the differential circuits CR1 to CR5 and the corresponding load circuits CH1 to CH6 for the first block        differential circuits CR2 to CR5 and corresponding load circuits CH2 to CH6 for each of the other blocks.        
To best ensure the regularity of the curves in the vicinity of the limits of the useful range with a view to an analog processing downstream, at least one additional differential circuit on each side and an associated load circuit is furthermore provided. For the first block (curve A), these additional circuits are the differential circuits CR0 and CR6 and the associated load circuits CH0 and CH7. For the other blocks, the additional circuits are the circuits CR1 and CR6 and the associated load circuits CH1 and CH7. Finally, to ensure global symmetry of the whole structure (and notably symmetry and homogeneity of the loads), matters are contrived so that there is the same number of differential circuits and of loads in all the blocks, thereby involving other additional circuits CR0 and CH0 for the three blocks providing the curves B, C, D. This enables all the curves A, B, C, D to have exactly the same amplitude and regularly spaced zero crossings.
Consequently, in the structure of FIG. 2, the differential circuits and load circuits defining the folding curves of the useful range are the circuits represented with bolder lines in the figure, and the additional circuits, which serve only to better adjust these curves, are represented by slender lines.
It is understood that the number of additional circuits is significant, and engenders high consumption of current and high bulk on the integrated circuit. Indeed, in the given example, there are 17 differential circuits and 21 load circuits establishing the desired folding functions and 11 differential circuits and 11 additional load circuits to improve these curves.